The AI-HDL is open to student participants from all academic institutions and community colleges globally.

Short answer: Yes! 

You do not need to have already formed a team to register. Teams will be made up of 3-5 students and constructed of students from various or similar backgrounds within the same degree level (community college, undergraduate, or graduate). Teams will compete with other teams with their corresponding degree level and will be evaluated accordingly.

Registration is free but required.

You may register independently or as part of a team.

• If you register as part of a team, you will be prompted to provide your team name along with the email addresses of team members.
• If you register independently, you will be matched with 2-4 other students based on factors including level of experience and field of study.

Registration Link

*Registration Closes on November 30, 2025.

The responsibilities and time commitment for AI-HDL mentors are:

• Estimated Time Commitment: 1 hour/week per assigned team, up to 5 teams per mentor.
• Weekly Meetings: Host a meeting with each assigned team to review progress, challenges, and next steps.
• Technical Guidance: Provide expert advice on Verilog and hardware design concepts.
• EDA Implementation: Guide students in testing Verilog code on Cadence EDA tools.
• Progress Tracking: Monitor students' weekly progress, using checklists and milestones.
• Project Planning: Help students create weekly goals and strategies.
• Documentation Review: Ensure students maintain proper documentation of their design process.
• Milestone Review: Provide feedback after analyzing students' designs for each milestone.
• Final Submission Review: Assist in the evaluation of final design submissions.

Sign up to be a mentor

League mentors will provide participants with a detailed project description. Participants will be tasked with designing a specific hardware architecture based on the description. The project description will include:

• High-level Overview and Functionality: An in-depth explanation of how the device operates, including any specific functions or features, and the expected behavior under various conditions.
• Detailed Architecture and Components: A precise definition of the device's inputs and outputs, including the type, size, and expected behavior of each signal. This section will also outline the design's key subsections and how they interconnect.

Teams are required to:

• Generate the hardware design using the Large Language Model (LLM). The Verilog code for the device must be generated via prompting LLM, although minor manual corrections are allowed.
• Verify their design at each design phase. The teams will be given a set of test benches to help with this. Teams are also encouraged to create their custom test bench to verify the sub-modules they design. 

After verifying the design with the test bench, teams must demonstrate the successful operation of the hardware design. Mentors will help guide students through this process.

For more information, see the Educational Resources section of this page.

All participants will receive guidance from their mentors, as well as live, in-person and virtual recorded webinars and tutorials. (To accommodate groups participating from different time zones, we will upload the recorded sessions for later access on the AI-HDL webpage.)

• Tutorials will include hands-on activities with mentors present to help teams complete the activities.
• Feedback will be collected from students after each tutorial session. The content of tutorials will be adjusted based on the feedback.
• Supplementary materials like slides, reference documents, code samples, etc. will be shared beforehand to allow preparation to enable more effective and interactive sessions.
• Participants will use a Discord forum for ongoing discussion, specifically for technical issues related to the tools.  

Link to the Discord

Participants will be provided with a comprehensive environment to design, simulate, and implement their projects.

• Access to AI-Language Models:
  • Each team will have access to LLMs, such as OpenAI's ChatGPT, Anthropic's Claude, Google's Gemini, Meta's Llama, etc. You will be trained in how to use and prompt the LLMs to generate the hardware design code.
• Hardware Simulation and Design Tools:
  • Teams will have access to industry-standard EDA tools by Cadence and Synopsys, as well as free and open-source tools provided by the league mentors for simulating, synthesizing, implementing, and evaluating their hardware designs.

Each team will submit documents and designs as they work toward milestones, with their mentor's guidance. During the milestone reviews, the submitted documents and designs will be evaluated and scored according to the test benches and Power, Performance, and Area (PPA) metrics. The progress of all the teams will be posted online, and the teams with the highest scores will receive an incremental prize.

You will receive specific directions and support from mentors for the submission process.

• Each team will create a GitHub profile and commit all changes to the project throughout the league.
• The accounts should be private, with limited access granted to the mentors and judges.
• You will submit a report, test bench results, and all the prompts used to generate the design as part of your documentation.
• After the final submission deadline, you will not be able to change the content of the GitHub repository.

To ensure a fair winner selection process, AI-HDL organizers have developed a scoring rubric to evaluate submissions based on several design factors: 

• Power, Performance, and Area (PPA) metrics
• Compatibility with the description and test bench
• Security of the final design
• Efficiency of prompts used to generate the design

Winners will be announced in May 2026.

The tentative timeline of AI-HDL is provided below, which includes 4 Design Phases (DPs), 4 Milestone Reviews (MRs), and a Final Review and Evaluation Phase. We will have mentor Office Hours (OHs) for each design phase.

2025

• September 22: Registration Opens
• October 30: Webinar 1: Overview of AI-HDL, Design Challenge, Tool Flow, Timeline, Rubric, and Submissions
• November 20: Webinar 2: Design Challenge Announcement and Overview
• December 18: Webinar 3: Base Design Implementation Demo and Q&A
• November 30: Registration Closes

2026

• January 15: League Starts with DP#1: Base Design Expansion
• January 29: MR#1 and OH#1
• February 12: DP#2: Design Evaluation and PPA Optimization
• February 26: MR#2 and OH#2
• March 12: DP#3: Security Evaluation and Threat Mitigation
• March 26: MR#3 and OH#3
• April 9: DP#4: Design Netlist to Chip Tapeout
• April 23: MR#4 and OH#4
• May 7: League Ends with Final Design Submission, Review, and Evaluations.
• May 14: Winner Announcement.

Weekly time commitment:

• 1-hour stand-up league meetings.
• 5 hours of project work time.
• Each team will determine its own schedule and work methods.

Required Equipment:

• Instruction and related tools are provided.
• Participants should have a computer/laptop and internet/wifi access.
   

At this time the AI-HDL does not offer course credits.

Educational Content

ARM

• ARM Education
• Accelerating Learning
• ArmEducationX

Cadence

• Full RTL2GDS Demo using Cadence Tools

Tiny Tape-out

• Tiny Tape-out
• Digital Hardware Design Guide
• Hardware Descriptive Language Design Guide

IEEE

• Universalization of IC Design
• Makerchips

ARM:

• What is an FPGA?
• What is an ASIC?
• What is a CPU Architecture?
• What is a System on a Chip (SoC)?
• What is Processor Security?

Branch Education:

• How does Computer Hardware Work?
• How are Microchips Made?
• What's Inside a Smartphone?

Additional Videos:

• An Introduction to Verilog
• Is it as important as Air?! | ‘Semiconductor Dictionary’ by Samsung Semiconductor
• Things You Didn’t Know About Semiconductor | ‘Semiconductor Dictionary’ by Samsung Semiconductor
• The Semiconductor Terms That You Must Know | 'All About Semiconductor' by Samsung Semiconductor
• Master the Perfect ChatGPT Prompt Formula (in just 8 minutes)!
• How Are Microchips Made?
• Inside the Making of an Intel Chip – 360 Fab Tour for VR

Additional Videos:

• Using Generative AI for ASIC Design
• Generative AI for HW Design and Verification
• AI Automated Chip Design? Will AI Replace Scientists in the Future? | THRESHOLD
• AI for Chip Design | NYU Tandon School of Engineering
• First chip designed with AI! An interview with Dr. Hammond Pearce & Jason Blocklove

ARM Early Careers

Faculty:

• Soheil Salehi, AI-HDL Founder, Assistant Professor of Electrical and Computer Engineering
• Pratik Satam, Assistant Professor of Systems and Industrial Engineering
• Janet Roveda, Professor of Electrical and Computer Engineering
• Liesl Folks, Professor of Electrical and Computer Engineering
• Rozhin Yasaei, Assistant Professor of Cyber Operations, Intelligence, and Technology
• Jyotikrishna Dass, Assistant Professor of Electrical and Computer Engineering
• Huanrui Yang, Assistant Professor of Electrical and Computer Engineering
• Krishna Muralidharan, Professor of Materials Science and Engineering, Director of the Center for Semiconductor Manufacturing 

Staff:

• Angela Cruze, Director of Programs and Operations, Office of the Chief AI Officer
• Amanda Harrell, Program Manager, Office of the Chief AI Officer
• Evelyn O'Neal, Communications and Marketing, Office of the Chief AI Officer

Students:

• Harish Kumar Dharavath, Ph.D. Student, Electrical and Computer Engineering
• Muhtasim Alam Chowdhury, Ph.D. Student, Electrical and Computer Engineering
• Sujan Ghimire, Ph.D. Student, Electrical and Computer Engineering
• Veeramani Pugazhenthi, M.S. Student, Electrical and Computer Engineering
• Thu Pham, B.S. Student, Electrical and Computer Engineering
• Anwar Gatto, B.S. Student, Optical Sciences

ACADEMIC INSTITUTIONS:

• The University of Arizona, USA
• University of Heidelberg, Germany
• Digital University of Kerala, India
• University of New South Wales, Australia
• Hanoi University of Science and Technology, Vietnam
• VNU University of Engineering and Technology, Vietnam

COMMUNITY COLLEGES:

• Pima Community College, USA
• Pasadena City College, USA