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AI Hardware Design League

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About AI-HDL Overview & FAQ Educational Resources Sponsorship Organizers

ABOUT AI-HDL

Can you imagine life without your smartphone, laptop, tablet, or the internet? These technologies all rely on semiconductors, and the semiconductor industry is booming. AI-HDL is your chance to take a leap into that world – no experience necessary! Imagine designing the next breakthrough chip using just your creativity and AI’s power. 

Watch the intro video to learn more about the semiconductor industry and AI-HDL.

 

 

5 Reasons to Join AI-HDL

1. Gain valuable knowledge.

If you’ve ever wondered “How does my smartphone work?” AI-HDL could be for you. In the league, you’ll work with the same type of technology the engineers use—building the future, one chip at a time.

2. Learn the basics of AI tools & hardware design. 

What are LLMs? What’s an FPGA board and how do I use it? You’ll get in-person trainings and guidance from a team mentor who will provide you with a solid foundation of knowledge and in-demand skills for the high-growth, high-impact semiconductor industry.

3. Meet new people & make friends. 

You can form a team or register solo. Either way, you get to connect with other students as you learn and innovate.

4. Experience how AI & hardware work together. 

Along with your teammates, use your creativity and the power of AI to start building the future and bring your ideas to life.

5. Discover incredible career opportunities.

Companies like ARM, Nvidia, Intel, and TSMC are seeking talent for roles in hardware engineering, process engineering, and more.

 

OVERVIEW & FAQ

  • PARTICIPATION & REGISTRATION

The AI-HDL is open to student participants from high schools, community colleges, and universities globally. Registration is free but required.

AI-HDL 2027 has two divisions. Teams compete against other teams in their division and are evaluated accordingly.

  • Lower Division is for high school teams. Every member of a Lower Division team must be a high school student.
  • Upper Division is for community college, undergraduate, and graduate teams. Upper Division teams may mix community college, undergraduate, and graduate students, with a maximum of 3 graduate students per team. Teams that include community college students receive bonus points.

Short answer: Yes! 

Teams are made up of 3-5 students at the same division level. You do not need to have already formed a team to register, and you may register independently or as part of a team.

  • If you register as part of a team, you will be required to provide your team name.
  • If you are the team captain, you will be required to provide the institutional email addresses of your team members. Every team member must still complete their own registration.
  • If you register independently, we will match you with a team at your institution that has fewer than 5 members, or connect you with 2-4 other students at your institution based on level of experience, background, field of study, and availability.
  • If you are registering for the Lower Division, you must provide the name and email of a teacher or faculty sponsor at your high school. This applies whether you register independently or as part of a team.

Registration Link

*Registration Closes on December 18, 2026.

The responsibilities and time commitment for AI-HDL mentors are:

  • Estimated Time Commitment: 1 hour/week per assigned team, up to 5 teams per mentor.
  • Weekly Meetings: Host a meeting with each assigned team to review progress, challenges, and next steps.
  • Technical Guidance: Provide expert advice on Verilog and hardware design concepts.
  • EDA Implementation: Guide students in testing Verilog code on EDA tools.
  • Progress Tracking: Monitor students' weekly progress, using checklists and milestones.
  • Project Planning: Help students create weekly goals and strategies.
  • Documentation Review: Ensure students maintain proper documentation of their design process.
  • Milestone Review: Provide feedback after analyzing students' designs for each milestone.
  • Final Submission Review: Assist in the evaluation of final design submissions.

Sign Up To Be A Mentor

League mentors will provide participants with a detailed project description. Participants will be tasked with designing a specific hardware architecture based on the description. The project description will include:

  • High-level Overview and Functionality: An in-depth explanation of how the device operates, including any specific functions or features, and the expected behavior under various conditions.
  • Detailed Architecture and Components: A precise definition of the device's inputs and outputs, including the type, size, and expected behavior of each signal. This section will also outline the design's key subsections and how they interconnect.

Teams are required to:

  • Generate the hardware design using the Large Language Models (LLMs). The Verilog code for the device must be generated via prompting the LLM, although minor manual corrections are allowed.
  • Verify their design at each design phase. The teams will be given a set of test benches to help with this. Teams are also encouraged to create their own test bench to verify the sub-modules they design. 

After verifying the design with the test bench, teams must demonstrate the successful operation of the hardware design. Mentors will help guide students through this process.

For more information, see the Educational Resources section of this page.

All participants will receive guidance from their mentors, as well as live and virtual recorded webinars and tutorials. (To accommodate groups participating from different time zones, we will upload the recorded sessions on the AI-HDL webpage.)

  • Tutorials will include hands-on activities with mentors present to help teams complete the activities.
  • Feedback will be collected from students after each tutorial session. The content of tutorials will be adjusted based on the feedback.
  • Supplementary materials like slides, reference documents, code samples, etc. will be shared beforehand to allow preparation and enable more effective and interactive sessions.
  • Participants will use a Discord forum for ongoing discussion, specifically for technical issues related to the tools.  

Link To The Discord

Participants will be provided with a comprehensive environment to design, simulate, and implement their projects.

  • Access to AI and Large Language Models (LLMs):
    • Each team will have access to LLMs, such as OpenAI's ChatGPT, Anthropic's Claude, Google's Gemini, Meta's Llama, etc. You will be trained in how to use and prompt the LLMs to generate the hardware design code.
  • Hardware Simulation and Design Tools:
    • Teams will have access to industry-standard EDA tools by Cadence and Synopsys, as well as free and open-source tools provided by the league mentors for simulating, synthesizing, implementing, and evaluating their hardware designs.

Each team will submit documents and designs as they work toward milestones, with their mentor's guidance. During the milestone reviews, the submitted documents and designs will be evaluated and scored according to the test benches and Power, Performance, Area, and Security (PPAS) metrics. 

You will receive specific directions and support from mentors for the submission process.

  • Each team will create a GitHub profile and commit all changes to the project throughout the league.
  • The accounts should be private, with limited access granted to the mentors and judges.
  • You will submit a report, test bench results, and all the prompts used to generate the design as part of your documentation.
  • After the final submission deadline, you will not be able to change the content of the GitHub repository.

To ensure a fair winner selection process, AI-HDL organizers have developed a scoring rubric to evaluate submissions based on several design factors: 

  • Power, Performance, Area, and Security (PPAS) metrics
  • Compatibility with the description and test bench
  • Efficiency of prompts used to generate the design

Winners will be announced in May 2027.

  • TIMELINE & DETAILS

The tentative timeline of AI-HDL is provided below, which includes 4 Design Phases (DPs), 4 Milestone Reviews (MRs), and a Final Review and Evaluation Phase. We will have mentor Office Hours (OHs) for each design phase.

2026

  • September 1: Registration Opens
  • October 29: Webinar 1: Overview of AI-HDL, Design Challenge, Tool Flow, Timeline, Rubric, and Submissions
  • November 19: Webinar 2: Design Challenge Overview, Base Design Implementation Demo, and Q&A
  • December 17: Webinar 3: ChipMango AI-HDL Certificate
  • December 18: Registration Closes

2027

  • January 14: League Starts with DP#1: Base Design Expansion
  • January 28: Webinar 4: TBD (MR#1 and OH#1)
  • February 11: DP#2: Design Evaluation and PPA Optimization
  • February 25: Webinar 5: TBD (MR#2 and OH#2)
  • March 11: DP#3: Security Evaluation and Threat Mitigation
  • March 25: Webinar 6: TBD (MR#3 and OH#3)
  • April 8: DP#4: Design Netlist to Chip Tapeout
  • April 22: Webinar 7: TBD (MR#4 and OH#4)
  • April 29: League Ends with Final Design Submission, Review, and Evaluations
  • May 6: Winner Announcement

Weekly time commitment:

  • 1-hour stand-up team meeting
  • 3-5 hours of project work time
  • Each team determines its own schedule and work methods

Required Equipment:

  • Instruction and related tools are provided.
  • Participants should have a computer/laptop and internet/wifi access.

At this time, the AI-HDL does not offer course credits. 

EDUCATIONAL RESOURCES

Educational Content

AI-HDL (EDA Tool Setup)

ARM

Cadence

Tiny Tape-out

IEEE

ARM:

Branch Education:

Additional Videos:

Additional Videos:

ARM Careers Opportunities

NVIDIA Career Opportunities

Cadence Career Opportunities

Synopsys Career Opportunities

SPONSORSHIP

sponsors

Sponsorship Opportunities

We are excited to partner with industry leaders to lower the barrier of entry to semiconductor manufacturing, and encourage excellence and innovation in our future innovators and tech leaders. Our sponsors play a crucial role in providing resources and opportunities, while receiving exposure and access to the next generation of hardware design and security professionals.

  • Student participants: Ensure diverse participation across various institutions.
  • Awards: Fund or donate prizes and recognition for top-performing teams.
  • Operations: Support the logistical and administrative costs of running a professional competition.
  • Equipment and Development Tools: Provide access or in-kind donations of necessary tools or hardware (e.g., Arduino hardware or FPGA boards).
  • Workshops: Ensure participants receive valuable skill development. 

 Please connect with our team to learn more!

 AI-HDL Sponsorship form

ORGANIZING TEAM AND PAST COMPETITORS

Faculty:

  • Soheil Salehi, AI-HDL Founder, Assistant Professor of Electrical, Computing, and Software Engineering, Fellow of the Center for Semiconductor Manufacturing
  • Pratik Satam, Assistant Professor of Systems and Industrial Engineering
  • Janet Roveda, Professor of Electrical, Computing, and Software Engineering, Fellow of the Center for Semiconductor Manufacturing

Students:

Staff:

  • Connie S. Gardner, Program Operations Manager, Center for Semiconductor Manufacturing
  • Rozanne Canizales, Administrative Manager, School of Electrical, Computing, and Software Engineering
  • Deya Mendivil, Administrative Support Assistant, School of Electrical, Computing, and Software Engineering
  • Vianca Federico, Administrative Support Assistant, School of Electrical, Computing, and Software Engineering
  • Zander Leon, Marketing and Data Coordinator, School of Electrical, Computing, and Software Engineering

ACADEMIC INSTITUTIONS:

  • The University of Arizona, USA
  • University of Heidelberg, Germany
  • Digital University of Kerala, India
  • University of New South Wales, Australia
  • Hanoi University of Science and Technology, Vietnam
  • VNU University of Engineering and Technology, Vietnam
  • University of Cincinnati, USA
  • San Francisco State University, USA
  • University of Illinois Urbana-Champaign, USA
  • University of Louisiana at Lafayette, USA
  • University of South Carolina, USA
  • University of Florida, USA
  • Florida International University, USA
  • Northeastern University, USA
  • Lamar University, USA
  • The University of Texas at El Paso, USA
  • Howard University, USA
  • New Mexico State University, USA
  • Portland State University, USA
  • KU Leuven, Belgium
  • University of Bremen, Germany
  • Ankara Yıldırım Beyazıt University, Türkiye
  • Yıldız Technical University, Türkiye
  • Indian Institute of Technology Delhi, India
  • College of Engineering Trivandrum, India
  • Indian Institute of Engineering Science and Technology, Shibpur, India
  • Bangladesh University of Engineering and Technology, Bangladesh
  • The American University in Cairo, Egypt
  • University of Cape Coast, Ghana
  • Regent University College of Science and Technology, Ghana
  • Mampong Technical College of Education, Ghana
  • Ashesi University, Ghana
  • Ghana Communication Technology University, Ghana
  • Jomo Kenyatta University of Agriculture and Technology, Kenya
  • Obafemi Awolowo University, Nigeria
  • Miva Open University, Nigeria
  • University of Lagos, Nigeria
  • Copperbelt University, Zambia

COMMUNITY COLLEGES:

  • Pima Community College, USA
  • Pasadena City College, USA
  • Des Moines Area Community College, USA
  • Santa Monica College, USA
  • Mercer County Community College, USA
  • Ivy Tech Community College, USA