The AI-HDL pilot is currently open to student participants from the following institutions:

• University of Arizona
• University of New South Wales
• Hanoi University of Science and Technology
• VNU University of Engineering and Technology
• Digital University of Kerala
• Heidelberg University
• Pima Community College
• Pasadena City College

Short answer: Yes! 

You do not need to have already formed a team to register. Teams will be made up of 3-5 students and constructed of students from various or similar backgrounds within the same degree level (community college, undergraduate, graduate). Teams will compete with other teams with their corresponding degree level and will be evaluated accordingly.

Registration is free but required.

You may register independently or as part of team.

• If you register as part of a team, you will be prompted to provide your team name along with email addresses of team members.
• If you register independently, you will be matched with 2-4 other students based on factors including level of experience, field of study.

Register Now

During the AI-HDL pilot, the league participation is limited to students and mentors from partner institutions. In the future we hope to scale the league and expand eligibility so more students can take part.

Join the next wave! Sign up to be notified about eligibility for the 2025-26 AI-HDL.

Sign up for 2025-26 AI-HDL notifications

The responsibilities and time commitment for AI-HDL mentors are:

• Estimated Time Commitment: 1-2hr/week per assigned team, up to 5 teams per mentor.
• Weekly Meetings: Host a meeting with each assigned team to review progress, challenges, and next steps.
• Technical Guidance: Provide expert advice on Verilog and hardware design concepts.
• FPGA Implementation: Guide students in testing Verilog code on FPGA boards.
• Progress Tracking: Monitor students' weekly progress, using checklists and milestones.
• Project Planning: Help students create weekly goals and strategies.
• Documentation Review: Ensure students maintain proper documentation of their design process.
• Milestone Review: Provide feedback after analyzing students' designs for each milestone.
• Final Submission Review: Assist in evaluation of final design submissions.

Sign up to be a mentor

League mentors will provide participants with a detailed project description. Participants will be tasked with designing a specific hardware architecture based on the description. The project description will include:

• High-level Overview and Functionality: An in-depth explanation of how the device operates, including any specific functions or features, and the expected behavior under various conditions.
• Detailed Architecture and Components: A precise definition of the device's inputs and outputs, including the type, size, and expected behavior of each signal. This section will also outline the design's key subsections and how they interconnect.

Teams are required to:

• Generate the hardware design using the Large Language Model (LLM). The Verilog code for the device must be generated via prompting LLM, although minor manual corrections are allowed. 
• Verify their design at each design phase. The teams will be given a set of test benches to help with this. Teams are also encouraged to create their custom test bench to verify the sub-modules they design. 

After verifying the design with the test bench, teams must demonstrate the successful operation of the hardware design on an FPGA board. Mentors will help guide students through FPGA implementation.

All participants will receive guidance from their mentors, as well as live, in-person and virtual recorded tutorials. (To accommodate groups participating from different time zones, we will upload the recorded sessions for later access on the AI-HDL webpage.)

• Tutorials will include hands-on activities with mentors present to help teams complete the activities.
• Feedback will be collected from students after each tutorial session. The content of tutorials will be adjusted based on the feedback.
• Supplementary materials like slides, reference documents, code samples, etc. will be shared before to allow preparation to enable more effective and interactive sessions.
• Participants will use a Discord forum for ongoing discussion, specifically for technical issues related to the tools.  
   

Participants will be provided with a comprehensive environment to design, simulate, and implement their projects.

• Access to AI-Language Models:
  • Each team will have access to LLMs such as OpenAI's ChatGPT. You will be trained in how to use and prompt the LLMs to generate the hardware design code.
• Hardware Simulation and Design Tools: 
  • Teams will use free tools provided by the league mentors for simulating, synthesizing, implementing, and evaluating their hardware designs.
  • Teams will be guided by mentors to implement their hardware designs on an FPGA board. This will take place during mentor meetings where mentors will have access to the FPGA board and will demonstrate to students how they can implement their designs on a real hardware environment, providing valuable hands-on experience.

Each team will submit documents and designs as work toward milestones, with their mentor's guidance. During the milestone reviews, the submitted documents and designs will be evaluated and scored according to the test benches and Power, Performance, and Area (PPA) metrics. The progress of all the teams will be posted online, and the teams with the highest scores will receive an incremental prize.

• Milestone 1: 25% of the design should be completed. (Teams are expected to have some initial results.)
• Milestone 2: 50% of the design should be completed. 
• Milestone 3: 75% of the design should be completed.
• Final Design Phase: 100% of the design should be completed. (Teams are expected to submit the final design and all the required documents for evaluation.)

You will receive specific directions and support from mentors for the submission process.

• Each team will create a GitHub profile and commit all changes to the project throughout the league.
• The accounts should be private, with limited access granted to the mentors and judges.
• You will submit a report, recorded presentation, test bench results, and all the prompts used to generate the design as part of your documentation.
• After the final submission deadline, you will not be able to change the content of the GitHub repository.

To ensure a fair winner selection process, AI-HDL organizers have developed a scoring rubric to evaluate submissions based on several design factors: 

• Power, Performance, and Area (PPA) metrics
• Compatibility with the description and test bench
• Successful FPGA implementation
• Efficiency of prompts used to generate the design
• Security of the final design.

Winners will be announced in early 2025.

The top rated designs will be fabricated through the Efabless chipignite program.

The tentative timeline of AI-HDL is provided below, which includes 3 Design Phases (DPs), 3 Milestone Reviews (MRs), and a Final Review and Evaluation Phase. We will have mentor Office Hours (OHs) for each design phase.

2024

• October 25: Kick-off Event
• October 31: Registration Closes
• November 1: League Starts with DP#1: Tool Setup and Initial Design Implementation
• November 22: MR#1 and OH#1
• December 1: DP#2: Additional Functionalities and Design Optimization
• December 20: MR#2 and OH#2

2025

• January 1: DP#3: Secure Implementation and Design Optimization
• January 24: MR#3 and OH#3
• January 31: Final Design Submission
• February 1: League Ends with Final Design Review and Evaluations.
• February 21: Winner Announcement.
   

Weekly time commitment:

• 1-2 hour stand-up league meetings.
• 5-10 hours of project work time.
• Each team will determine its own schedule and work methods.

Required Equipment:

• Instruction and related tools are provided.
• Participants should have a computer/laptop and internet/wifi access.
   

At this time the AI-HDL does not offer course credits.

Educational Content

ARM

• ARM Education
• Accelerating Learning
• ArmEducationX

EFabless

• Tiny Tape-out 
• Digital Hardware Design Guide
• Hardware Descriptive Language Design Guide

IEEE

• Universalization of IC Design
• Makerchips

Tutorial Content

Coming Soon!

ARM:

• What is an FPGA?
• What is an ASIC?
• What is a CPU Architecture?
• What is a System on a Chip (SoC)?
• What is Processor Security?

Branch Education:

• How does Computer Hardware Work?
• How are Microchips Made?
• What's Inside a Smartphone?

Additional Videos:

• An Introduction to Verilog
• Is it as important as Air?! | ‘Semiconductor Dictionary’ by Samsung Semiconductor
• Things You Didn’t Know About Semiconductor | ‘Semiconductor Dictionary’ by Samsung Semiconductor
• The Semiconductor Terms That You Must Know | 'All About Semiconductor' by Samsung Semiconductor
• Master the Perfect ChatGPT Prompt Formula (in just 8 minutes)!
• How Are Microchips Made?
• Inside the Making of an Intel Chip – 360 Fab Tour for VR

EFabless:

• Using Generative AI for ASIC Design
• Generative AI for HW Design and Verification

Additional Videos:

• AI Automated Chip Design? Will AI Replace Scientists in the Future? | THRESHOLD
• AI for Chip Design | NYU Tandon School of Engineering
• First chip designed with AI! An interview with Dr. Hammond Pearce & Jason Blocklove

ARM Early Careers

• Soheil Salehi, AI-HDL Founder and Lead, Assistant Professor of Electrical and Computer Engineering
• Angela Cruze, Director of Programs and Operations, Institute for Computation and Data-enabled Insights
• Janet Roveda, Professor of Electrical and Computer Engineering
• Liesl Folks, VP of Semiconductor Strategy, Director of Center for Semiconductor Manufacturing 

Faculty

• Pratik Satam, Assistant Professor of Systems and Industrial Engineering
• Banafsheh Saber Latibari, Postdoctoral Associate, Electrical and Computer Engineering
• Ali Akoglu, Professor of Electrical and Computer Engineering
• Tosiron Adegbija, Associate Professor of Electrical and Computer Engineering
• Xiaodong Yan, Assistant Professor of Material Science and Engineering
• Huanrui Yang, Assistant Professor of Computer Science and Engineering
• Jyotikrishna Dass, Assistant Professor of Electrical and Computer Engineering
• Bo Liu, Associate Professor of Electrical and Computer Engineering
• Han Xu, Assistant Professor of Electrical and Computer Engineering
• Rozhin Yasaei, Assistant Professor of Cyber Operations, Intelligence, and Technology
• Dale Hetherington, Professor of Practice, Electrical and Computer Engineering
• Ratchaneekorn "Kay" Thamvichai, Professor of Practice, Electrical and Computer Engineering

Staff 

• Amanda Harrell, Program Manager, Institute for Computation and Data-enabled Insights
• Meaghan Miller, Communications, Center for Semiconductor Manufacturing
• Dan Moseke, Project Director, Center for Semiconductor Manufacturing
• Connie Gardner, Program Operations Manager, Center for Semiconductor Manufacturing
• Susan Novosel, Marketing Information and Data Coordinator, Electrical and Computer Engineering

• Muhtasim Alam Chowdhury, Research Assistant/PhD student, Electrical and Computer Engineering
• Sujan Ghimire, Research Assistant/PhD student, Systems and Industrial Engineering
• Yu-Zheng Lin, Research Assistant/PhD student, Systems and Industrial Engineering
• Muntasir Mamun, Research Assistant/PhD student, Systems and Industrial Engineering
• Jaeden Carpenter, Research Assistant/MS student, Electrical and Computer Engineering
• Christopher Mastrangelo, Research Assistant/MS student, Electrical and Computer Engineering
• Ricardo Ramirez, Research Assistant/MS student, Electrical and Computer Engineering 
• Reshma Sai Yarlagadda, Research Assistant/MS student, Information Science
• Anand Ramaswamy Jayshree, Research Assistant/MS student, Information Science
• Emma Heckert, Research Assistant/BS student, Electrical and Computer Engineering
• William Rains, Research Assistant/BS student, Electrical and Computer Engineering
• Malcolm Hayes, Research Assistant/BS student, Electrical and Computer Engineering
• Anwar Gatto, Research Assistant/BS student, Electrical and Computer Engineering
• Ernesto Martinez, Research Assistant/BS student, Electrical and Computer Engineering

• Hammond Pearce, Lecturer (Assistant Professor) of Computer Science and Engineering, University of New South Wales
• Alex James, Dean and Professor of Electronic Systems and Automation, Digital University Kerala
• Nima Taherinejad, Professor of Institute of Computer Engineering, Heidelberg University
• Nguyen Vu Thang, Lecturer and Deputy Head of Academic Office, Hanoi University of Science and Technology
• Anh Tuan Mai, Associate Professor of Computer Engineering, VNU University of Engineering and Technology

Community College

Pima Community College
Central Arizona College
Pasadena City College

High School

Basis High School
Catalina Foothills High School
Chandler Unified School District
Sunnyside School District
Tucson High School