When
This IEEE Council on Electronic Design Automation (CEDA) panel discussion, part of the CAD Assurance for series, is moderated by CSM Fellows Rozhin Yasaei and Banafsheh Saber Latibari. 11:30am EDT.
As the semiconductor industry confronts the limitations of traditional scaling, heterogeneous integration emerges as a promising avenue to enhance performance and functionality beyond conventional system-on-chip (SoC) designs. However, this approach also introduces significant security challenges, particularly concerning the protection of hardware IP. The increased complexity of integrating diverse components into a single system creates new vulnerabilities and threats across the design, manufacturing, and integration processes. This panel will focus on addressing these security challenges, exploring specific threats such as IP theft, counterfeiting, tampering, and reverse engineering. We will also discuss strategies for safeguarding IP across the entire design stack within the physical design framework of heterogeneous integration, ensuring comprehensive protection across the semiconductor supply chain.
Panelists for this presentation include:
Farinaz Koushanfar – UC San Diego
Todd Austin – University of Michigan
Ahmadreza Sadeghi – TU Darmstadt
Qiaoyan Yu – NSF
John Oakley – SRC
Sandhya Koteshwara – IBM Research